In the conventional technology, an IC chip is connected with an external circuit by metal wire bonding. With reduction in feature sizes of IC chips and an expansion of scales of integrated circuits, the wire bonding technology is no longer suitable.
The wafer level chip size packaging (WLCSP) technology is a technology of packaging and testing a whole wafer and then cutting the whole wafer to acquire single finished chips, where the size of the packaged chip is the same as the size of a bare chip. The wafer level chip size packaging technology overturns the traditional packaging manners such as the ceramic leadless chip carrier packaging manner and the organic leadless chip carrier packaging manner, and meets market requirements for microelectronic products which are increasingly lighter, smaller, shorter, thinner and cheaper. A chip packaged with the wafer level chip size packaging technology is highly miniaturized, and the cost of the chip is greatly reduced with reduction of the size of the chip and an increase in the size of the wafer. The wafer level chip size packaging technology integrates IC design, wafer fabrication, and package test, and is a focus and a development trend of the current field of packaging.
An image sensor chip is capable of converting an optical image into an electronic signal, and includes a sensing region. In a case where the image sensor chip is packaged using the existing wafer level chip size packaging technology, an upper cover substrate is generally formed on the sensing region to protect the sensing region from being damaged or contaminated during a packaging process. The upper cover substrate may be retained after the wafer level chip size packaging for continuing protecting the sensing region from being damaged or contaminated during use of the image sensor chip.